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| Ordering number : EN6037 CMOS IC LC72723, LC72723M RDS Demodulation IC Overview The LC72723 is an RDS (Radio Data System) signal demodulation IC. This IC integrates a bandpass filter, the demodulation circuit, and buffer RAM on a single chip and can read out RDS data in slave mode operation with the provision of an external clock input. It also supports master mode, in which the data is read out in synchronization with an RDS clock output provided by the IC itself. Package Dimensions unit: mm 3006B-DIP16 [LC72723] 16 9 7.62 6.4 1 19.2 8 Functions * Bandpass filter: Switched capacitor filter (SCF) * RDS demodulation: Functions include 57kHz carrier regeneration, clock regeneration, biphase decoding, and differential decoding * Buffer RAM: Stores 128 bits (about 100 ms) of data. * Data output: Output can be switched between master mode and slave mode readout. * RDS ID detection: Supports ID reset * Standby control: Stops the crystal oscillator. * Fully adjustment free. 0.71 2.54 0.48 1.2 3.4 3.65max 3.0 SANYO: DIP16 unit: mm 3035A-MFP16 [LC72723M] 16 9 0.625 Ratings * Operating supply voltage: 4.5 to 5.5 V * Operating temperature: -40 to 85C * Packages: DIP16 and MFP16 1 10.1 1.5 8 5.15 6.4 4.4 1.8max 0.15 0.35 1.27 0.605 0.1 SANYO: MFP16 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 40299RM (OT) No. 6037-1/8 0.25 LC72723, LC72723M Pin Assignment (DIP16/MFP16) Block Diagram No. 6037-2/8 LC72723, LC72723M Pin Descriptions Pin No. Pin Function I/O Pin circuit type 1 VREF Reference voltage output (Vdda/2) Output 2 MPXIN Base band (multiplex) signal input Input 5 FLOUT Subcarrier output (filter output) Output 6 CIN Subcarrier input (comparator input) Input 3 4 8 Vdda Vssa XOUT Analog system power supply (+5 V) Analog system ground Crystal element output (4.332 MHz) -- -- Output -- -- 9 XIN Crystal element input (or external reference signal input) 7 12 13 TEST MODE RST Test input Readout mode setting (0: master, 1: slave) RDS ID and RAM reset (Active high logic) Input 14 RDDA RDS data output Output 15 RDCL RDS clock output (master mode) RDS clock input (slave mode) I/O 16 RDS-ID/READY RDS ID/ready output (Active low) Output 11 10 Vddd Vssd Digital system power supply (+5 V) Digital system ground -- -- -- -- No. 6037-3/8 LC72723, LC72723M Specifications Absolute Maximum Ratings at Ta = 25C, Vssd = Vssa = 0 V Parameter Maximum supply voltage Symbol VDD max VIN1 max Maximum input voltage VIN2 max VIN3 max Vo1 max Maximum output voltage Vo2 max Vo3 max Maximum output current Io1 max Io2 max Pd max Topr Tstg Vddd, Vdda * TEST, MODE, RST XIN, RDCL MPXIN, CIN RDS-ID (READY) XOUT, RDDA, RDCL FLOUT XOUT, FLOUT, RDDA, RDCL RDS-ID (READY) (Ta 85C) Conditions Ratings -0.3 to 7.0 -0.3 to +7.0 -0.3 to Vddd + 0.3 -0.3 to Vdda + 0.3 -0.3 to +7.0 -0.3 to Vddd + 0.3 -0.3 to Vdda + 0.3 +3.0 +20.0 DIP16 : 300 MFP16 : 140 -40 to +85 -55 to +125 Unit V V V V V V V mA mA mW mW C C Allowable power dissipation Operating temperature Storage temperature *: Note that Vdda must be less than or equal to Vddd + 0.3 V Allowable Operating Ranges at Ta = -40 to +85C, Vssd = Vssa = 0 V, Vddd = Vdda Parameter Supply voltage High-level input voltage Low-level input voltage Output voltage Symbol VDD VIH1 VIH2 VIL Vo1 Vo2 VIN1 Input amplitude VIN2 VXIN Guaranteed oscillator operating range Crystal oscillator frequency deviation RDCL setup time RDCL high-level time RDCL low-level time Data output time READY output time READY low-level time Xtal TXtal tCS tCH tCL tDC tRC tRL Conditions Vddd, Vdda: Vddd = Vdda TEST, MODE, RST RDCL TEST, MODE, RST, RDCL RDDA, RDCL RDS-ID (READY) f = 57 2 KHz MPXIN XIN XIN, XOUT: C1 120 XIN, XOUT: Fo = 4.332 MHz RDCL, RDDA RDCL RDCL RDCL, RDDA RDCL, READY READY 0 0.75 0.75 0.75 0.75 107 100% modulation, composite 100 400 4.332 100 1500 Ratings min 4.5 07 Vddd 0.7 Vddd 0 typ 5.0 max 5.5 6.5 Vddd 0.3 Vddd Vddd 6.5 50 Unit V V V V V V mVrms mVrms mVrms MHz ppm s s s S s ms No. 6037-4/8 LC72723, LC72723M Electrical Characteristics at Ta = -40 to +85C, Vssd = Vssa = 0 V, Vddd = Vdda Parameter Symbol Rmpxin Rcin Rf fc BW-3dB Gain Att1 Stop band attenuation Att2 Att3 Reference voltage output Hysteresis Low-level output voltage High-level output voltage High-level input current Vref VHIS VOL1 VOL2 VOH IIH1 IIH2 IIL1 IIL2 IOFF Idd Conditions MPXIN-Vssa: f = 57 KHz CIN-Vssa: f = 57 KHz XIN FLOUT FLOUT MPXIN-FLOUT: f = 57 KHz FLOUT: f = 7 KHz FLOUT: f < 45 KHz, f > 70 KHz FLOUT: f < 20 KHz Vref: Vdda = 5 V TEST, MODE, RST, RDCL RDDA, RDCL : I = 2 mA RDS-ID (READY): I = 8 mA RDDA, RDCL : I = 2 mA TEST, MODE, RST, RDCL : VI = 6.5 V XIN: VI = Vddd TEST, MODE, RST, RDCL : VI = 0 V XIN: VI = 0 V RDS-ID (READY): VO = 6.5 V Vddd + Vdda 8 2.0 2.0 Vddd - 0.4 5.0 11 5.0 11 5.0 56.5 2.5 28 30 40 50 2.5 0.1 Vddd 0.4 0.4 Ratings min typ 23 100 1.0 57.0 3.0 31 57.5 3.5 34 max Unit K K M KHz KHz dB dB dB dB V V V V V A A A A A mA Input resistance Internal feedback resistance Center frequency -3dB bandwidth Gain Low-level input current Output off leakage current Current drain Inputs and Outputs TEST 0 0 1 1 MODE 0 1 0 1 Master mode Slave mode Standby mode (crystal oscillator stopped) IC test mode (Cannot be set by users.) Circuit operating mode RDCL pin Clock output Clock input -- -- RDS-ID/READY pin RDS-ID output READY output -- -- RST pin RST = 0 RST = 1 Normal operation The RDS-ID and demodulation circuits are cleared, and (in slave mode) the READY state and memory are cleared. RDS ID/READY pin Master mode RDS-ID output (active low) Slave mode Readout data ready output (active low) Note: The RDS-ID (READY) pin is an n-channel open-drain output, and data is read out by connecting a pull-up resistor. No. 6037-5/8 LC72723, LC72723M RDCL/RDDA Output Timing * Master mode RST Operation * Master mode Caution: After an RST input, the RDCL and RDDA outputs stop at the high level until the first RDS ID detection. RDCL Control in Slave Mode Parameter RDCL setup time RDCL high-level time RDCL low-level time Data output time READY output time Ready low-level time Symbol tCS tCH tCL tDC tRC tRL RDCL, RDDA RDCL RDCL RDCL, RDDA RDCL, READY READY Conditions Ratings min 0 0.75 0.75 0.75 0.75 107 typ max Unit s s s s s ms Notes:1. Start RDCL clock input after the READY signal goes low. Applications must stand by with RDCL held low when the READY pin is high. 2. Each time the RDCL input is switched from low to high to low, the application must check the READY signal level after the period tRC has elapsed once RDCL has been set low. If READY is at the low level, the application may apply the next RDCL clock cycle. If READY is high, the application must stop RDCL input at that point. 3. When the above timing conditions are met, RDDA can be read at either the rise or fall of the RDCL signal. 4. After the last data from memory has been read, READY will be high once the period tRC has elapsed after the fall of the RDCL signal. If even 1 bit of data has been written to memory, READY will be low and the application will be able to read that data. No. 6037-6/8 LC72723, LC72723M 5. When switching channels, it is desirable to immediately reset memory and the READY pin with an RST input. If this is not done, data received on the previous channel may remain in memory. When the IC is reset, data is not written until the RDS-ID is detected, and therefore, the READY signal will go low after the RDS-ID is detected. (Although the RDS-ID is not output in slave mode, it is detected internally in the IC.) After an RST input, once an RDSID has been detected, all received data will be written to memory regardless of the RDS-ID detection state. 6. The readout mode may be switched between master and slave modes during readout. Applications must observe the following points to assure data continuity during this operation. * Data acquisition timing in master mode Data must be read on the falling edge of RDCL. * Timing of the switch from master mode to slave mode After the RDCL output goes low and the RDDA data has been acquired, the application must set MODE high immediately. Then, the microcontroller starts output by setting the RDCL signal low. The microcontroller RDCL output must start within 840 s (tms) after RDCL went low. In this case, if the last data read in master mode was data item n, then data starting with item n+1 will be written to memory. * Timing of the switch from slave mode to master mode After all data has been read from memory and READY has gone high, the application must then wait until READY goes low once again the next time (timing A in the figure), immediately read out one bit of data and input the RDCL clock. Then, at the point READY goes high, the microcontroller must terminate RDCL output and then set MODE low. The application must switch MODE to low within 840 s (tms) after READY goes low (timing A in the figure). RDCL (microcontroller status) RDCL (IC status) No. 6037-7/8 LC72723, LC72723M LC72723 Sample Application Connection Circuit (for slave mode operation) Caution: If the RST pin is unused, it must be connected to ground. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 1999. Specifications and information herein are subject to change without notice. PS No. 6037-8/8 |
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